Description
H5TQ4G63EFR-TEC Hynix DDR3 SDRAM 4Gbit 1.425V~1.575V 1.066GHz FBGA-96, Auto self-refresh;Auto precharge function;Asynchronous reset function;Data mask function;Dynamic on-chip termination;ZQ calibration function;Write leveling function
Memory Size: 4Gbit DDR3 SDRAM
Voltage – Supply: 1.425V~1.575V
Clock Frequency: 1.066GHz
Packaging: Tray
Manufacturer PN: H5TQ4G63EFR-TEC
Manufacturer: HYNIX
Status Discontinued
Access Mode MULTI BANK PAGE BURST
Additional Feature AUTO/SELF REFRESH
JESD-30 Code R-PBGA-B96
Length (mm) 13.0000
Memory Density (bits) 4294967296.0000000000000000
Memory IC Type DDR3 DRAM
Memory Width 16
Number of Functions 1
Number of Ports 1
Number of Terminals 96
Number of Words (words) 268435456.0000000000000000
Number of Words Code 256M
Operating Mode SYNCHRONOUS
Operating Temperature-Max (Cel) 95.0
Operating Temperature-Min (Cel) 0.0
Memory Organization 256MX16
Package Body Material PLASTIC/EPOXY
Package Code TFBGA
Package Shape RECTANGULAR
Package Style GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Cel) NOT SPECIFIED
Seated Height-Max (mm) 1.2000
Self Refresh YES
Supply Voltage-Max (V) 1.57500
Supply Voltage-Min (V) 1.42500
Supply Voltage-Nom (V) 1.5
Surface Mount YES
Technology CMOS
Temperature Grade OTHER
Terminal Form BALL
Terminal Pitch (mm) 0.800
Terminal Position BOTTOM
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Width (mm) 7.5000
The H5TQ4G83EFR-xxC,H5TQ4G63EFR-xxC, H5TQ4G83EFR-xxI, H5TQ4G63EFR-xxI, H5TQ4G83EFR-xxL, H5TQ4G63EFR-xxL, H5TQ4G83EFR-xxJ, H5TQ4G63EFR-xxJ, H5TQ4G83EFR-xxK and H5TQ4G63EFR-xxK are a 4,294,967,296-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK Hynix 4Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
